There are many commercially successful non-volatile memory products being used today, particularly in the form of small form factor cards, which employ an array of flash EEPROM (Electrically Erasable and Programmable Read Only Memory) cells. A memory controller is also included in the card for interfacing with a host to which the card is connected and for controlling operation of the memory array within the card. Such a controller typically includes a microprocessor, some non-volatile read-only-memory (ROM) and a volatile random-access-memory (RAM). Besides the memory card implementation, this type of memory system, in the form of one or more integrated circuits, can alternatively be embedded into various types of host systems.
Two general memory cell array architectures have found commercial application, NOR and NAND. In a typical NOR array, memory cells are connected between adjacent bit line source and drain diffusions that extend in a column direction with control gates connected to word lines extending along rows of cells. A memory cell includes at least one storage element positioned over at least a portion of the cell channel region between the source and drain. A programmed level of charge on the storage elements thus controls an operating characteristic of the cells, which can then be read by applying appropriate voltages to the addressed memory cells. Examples of such cells, their uses in memory systems and methods of manufacturing them are given in U.S. Pat. Nos. 5,070,032, 5,095,344, 5,313,421, 5,315,541, 5,343,063, 5,661,053 and 6,222,762.
The NAND array utilizes series strings of more than two memory cells, such as 16 or 32, connected along with one or more select transistors between individual bit lines and a reference potential to form columns of cells. Word lines extend across cells within a large number of these columns. An individual cell within a column is read and verified during programming by causing the remaining cells in the string to be turned on hard so that the current flowing through a string is dependent upon the level of charge stored in the addressed cell. Examples of NAND architecture arrays and their operation as part of a memory system are found in U.S. Pat. Nos. 5,570,315, 5,774,397, 6,046,935, and 6,522,580.
The charge storage elements of current flash EEPROM arrays, as discussed in the foregoing referenced patents and articles are most commonly electrically conductive floating gates, typically formed from doped polysilicon material. Another type of memory cell useful in flash EEPROM systems utilizes a non-conductive dielectric material in place of a conductive floating gate to store charge in a non-volatile manner. Such a cell is described in an article by Chan et al., “A True Single-Transistor Oxide-Nitride-Oxide EEPROM Device,” IEEE Electron Device Letters, Vol. EDL-8, No. 3, March 1987, pp. 93-95. A triple layer dielectric formed of silicon oxide, silicon nitride and silicon oxide (“ONO”) is sandwiched between a conductive control gate and a surface of a semi-conductive substrate above the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where they are trapped and stored in a limited region, and erased by injecting hot holes into the nitride. Several specific cell structures employing dielectric storage elements are described in U.S. patent application Ser. No. 10/280,352, filed Oct. 25, 2002, publication no. 2003-0109093.
As in most all integrated circuit applications, the pressure to shrink the silicon substrate area required to implement some integrated circuit function also exists with flash EEPROM memory cell arrays. It is continually desired to increase the amount of digital data that can be stored in a given area of a silicon substrate, in order to increase the storage capacity of a given size memory card and other types of packages, or to both increase capacity and decrease size. One way to increase the storage density of data is to store more than one bit of data per memory cell and/or per storage element. This is accomplished by dividing a window of a storage element charge level voltage range into more than two states. The use of four such states allows each cell to store two bits of data, eight states stores three bits of data per storage element, and so on. Multiple state flash EEPROM structures using floating gates and their operation are described in U.S. Pat. Nos. 5,043,940 and 5,172,338, and for structures using dielectric floating gates in aforementioned U.S. application Ser. No. 10/280,352. Selected portions of a multi-state memory cell array may also be operated in two states (binary) for various reasons, in a manner described in U.S. Pat. Nos. 5,930,167 and 6,456,528.
Memory cells of a typical flash EEPROM array are divided into discrete blocks of cells that are erased together. That is, the block is the erase unit. Each block typically stores one or more pages of data, the page being the minimum unit of programming and reading, although more than one page may be programmed or read in a single operation. Each page typically stores one or more sectors of data, the size of the sector being defined by the host system. An example sector includes 512 bytes of user data, following a standard established with magnetic disk drives, plus some number of bytes of overhead information about the user data and/or the block in which they are stored. Memory systems are typically configured with 16, 32 or more pages within each block, and each page stores one or just a few host sectors of data.
The controller in a flash memory system typically includes a microprocessor that executes instructions from a firmware operating system, in order to control operation of the memory array and the flow of data between the array and the host system. In some commercial products, this firmware is stored in a small flash EEPROM as part of the controller, typically an integrated circuit chip that is separate from one or more memory cell array integrated circuit chips. The use of a flash memory allows the firmware to be easily updated by re-programming. The firmware is typically read from the flash memory and into the controller RAM upon the system either being powered up or reset. A small amount of booting code stored in the controller ROM is initially executed by the controller microprocessor to load the firmware into RAM. The microprocessor then executes instructions of the firmware from the RAM, since a type of such a memory may be used that can be read much faster than the flash memory. The RAM is, of course, volatile but if power is lost, the firmware is again loaded from the flash memory into the RAM upon power being restored and operation of the memory system is resumed.
Although this firmware booting system operates quite well, the controller integrated circuit chip is expensive because a different process must be used to form the flash memory than is used to form the remaining circuits on the chip. It has therefore been suggested, in order to reduce product cost, to store the firmware in designated blocks of the flash memory cell array that are not allowed to be accessed by the host to store user data. Upon system initialization, the controller microprocessor executes the ROM boot code to load the firmware into the RAM from designated blocks of flash memory. This still allows nearly all the firmware to be changed and updated by re-programming into those flash blocks since only a small amount of code is stored in the ROM for loading the firmware.